1. Field of the Invention
The present invention relates to a semiconductor storage device comprising a memory cell, a bit line connected to the memory cell, and a step-down circuit which steps down a potential of the bit line up to a predetermined voltage level lower than a power supply voltage before data is read from the memory cell.
2. Description of the Related Art
In the field of a semiconductor storage device, there is a conventional technology in which, for the purpose of improving a data reading speed, a bit line precharged with a power supply voltage is stepped down up to a predetermined voltage level lower than the power supply voltage before data is read, so that a period of time required for a voltage level in the bit line to change from the power supply voltage level to the ground level is shortened. The change from the power supply voltage level to the ground level in the bit line is detected by a PMO transistor provided at a subsequent gate. However, when a step-down level in the bit line is below the operation region of a transistor for detection, through current and a data-read error may occur. A data-read error also occurs in the case where a sense amplifier or a PMOS cross driver is connected to the bit line. Therefore, it is necessary to step-down the voltage of the bit line to around a threshold voltage of the PMOS transistor.
In a DRAM circuit where the bit line is precharged at the power supply voltage level, charges at the power supply voltage level of the bit line flow into a node of the SRAM at which “L” data is retained upon the activation of a word line, in a non-selected column operated when data is being read or written. The inflow of too many charges results in the occurrence of a data-write error. There is an indicator called a static noise margin as an indicator which shows a level of resistance against the data-write error.
In recent years, a static noise margin has been decreasing as the miniaturization of a semiconductor structure is advanced, and there is an increasing demand for the assurance of a certain static margin. As a response to the recent demand, there is a conventional technology wherein a potential of the bit line at the power supply voltage level is stepped down so as to reduce the flow of current from the bit line into the node of the memory cell at which “L” data is stored when the word line is activated. In the case where a step-down of the bit line is not enough, a data-write error occurs due to the reason described above. On the other hand, in the case where the step-down is excessive, a data-write error is caused by charges of “L” level of the bit line which flow into the node of the SRAM at which “H” data is retained. Therefore, it is necessary for a step-down level in the bit line to be at most such a voltage level that can assure the static noise margin and at least such a voltage level that does not result in the destruction of data.
Below is described a technology for the step-down operation in the bit line in a semiconductor storage device relating to the present invention referring to FIG. 24. FIG. 24A is a circuit diagram illustrating a constitution of a semiconductor storage device relating to the present invention, and FIG. 24B is a timing chart illustrating an operation of the semiconductor storage device.
In FIG. 24A, 11 denotes a SRAM memory cell, 12 denotes a precharge circuit, 13 denotes a reading circuit, 14 denotes a step-down circuit, BL and BL− denote complementary bit lines, WL denotes a word line, PC denotes a precharge control signal, DC denotes a step-down control signal, QP1, QP2 and QP3 denote PMOS transistors constituting the precharge circuit 12, QN11, QP11 and QP12 denote NMOS transistors constituting the step-down circuit 14.
The step-down circuit 14 is provided in order to perform the step-down operation for the bit lines BL and BL− prior to the activation of the word line WL. Sources of the step-down transistors QP11 and QP12 are connected to the ground, drains thereof are driven by the step-down control signal DC.
As illustrated in FIG. 24B, prior to the activation of the word line WL, the precharge control signal PC is negated and turns to “H” level at a timing t51, the precharge transistors QP1 and QP2 and the equalizing transistor QP3 are turned off, which leaves the bit lines BL and BL− in floating state.
At a timing t52, the step-down control signal DC is asserted and turns to “L” level, and the step-down transistors QP11 and QP12 in the step-down circuit 14 are turned on, and the equalizing transistor QN11 is turned on. Then, charges of the bit line BL and BL− are then discharged, and potentials of the bit lines BL and BL− are stepped down to a predetermined voltage level. A possible example of the predetermined voltage level is VDD-Vth. VDD is a power supply voltage used for the precharge, and Vth is a threshold voltage of the MOS transistors.
When the step-down control signal DC is negated and turns to “H” level at a timing t53, the step-down transistors QP11 and QP12 are turned off, and the equalizing transistor QN11 is turned off. As a result, the step-down and equalizing operations for the bit lines BL and BL− are halted.
At a timing t54, the word line WL is asserted, and data is read from the memory cell 11. In the case where “0” is stored in the memory cell 11, current flows from the bit line BL into the memory cell 11, and the potential of the bit line BL is lowered; however, the potential of the complementary bit line BL− is not lowered. The fact that the bit line BL=“L” level and the complementary bit line BL−=“H” level is read out and judged as “0” data by the reading circuit 14. In the case where “1” is stored in the memory cell 11, the current flows from the complementary bit line BL− into the memory cell 11, and the potential of the complementary bit line BL− is lowered; however, the potential of the bit line BL is not lowered. The fact that the bit line BL=“H” level and the complementary bit line BL−=“L” level is read out and judged as “1” data by the reading circuit 14. Broken lines denoting the potentials of the bit lines BL and BL− in FIG. 24B illustrate the potential reduction irrespective of whether it happens to the bit line BL or the complementary bit line BL−.
At a timing t55, the word line WL is at “L” level, and the data reading operation is terminated. At a timing t56, the precharge control signal PC is asserted and turns to “L” level, and the precharge transistors QP1 and QP2 and the equalizing transistor QP3 are turned on. Then, the bit lines BL and BL− are precharged with the power supply voltage.
When the semiconductor storage device thus constituted is activated, the step-down levels of the bit lines BL and BL− are adjusted in accordance with a pulse width of the step-down control signal DC. Provided that the step-down level is ΔV, and the pulse width of the step-down control signal DC is Tw, ΔV∝Tw, which means that the step-down level ΔV is substantially in proportion with the pulse width Tw of the step-down control signal DC.
Conventionally, the step-down operation for the bit line is performed in an initial stage of an operation cycle prior to the activation of the word line. Because the word line is activated in a short period of time after the start of the cycle, the step-down transistor is controlled based on the step-down control signal having a very small pulse width. In the conventional technology, the step-down level ΔV in the bit line is set based on the pulse width Tw of the step-down control signal DC inputted to the step-down transistors QP11 and QP12. Therefore, when the pulse width Tw of the step-down control signal DC is changed due to operation conditions or variability in devices, a large difference is generated in the step-down level ΔV, which results in malfunctioning.
Along with the miniaturization of a semiconductor memory circuit, the load capacity of a bit line and the pulse width of a step-down control signal exhibit a relatively wider range of variability. As a result, it is increasingly difficult to compensate for the step-down level in the bit line.
Further, a bit line step-down circuit and control circuit which controls the step-down operation occupy a larger area, as a result of which a circuit layout area and a reading speed are unfavorably increased.